[computer-go] Go hardware?

[Chrilly]

I thought about to build such a machine into a big FPGA. Lets say 128 
softprocessors which are controlled by the ARM-core of the FPGA. Building a 
softprocessor is relativ trivial. It need not have the quirks of the 0x88. 
The "natural" size in a XiLinx FPGA is a 16-Bit processor with a 18 Bit 
instruction word (the FPGA BlockRAM is 18 bits wide).
I have already designed the CR16 processor with Assembler and C-Simulator 
and as a benchmark a chess move generator.
The problem is to coordinate a massive parallel system. Thats not at all 
trivial. So far such systems are SIMD (Single-Instruction Multiple Data). 
One master generates the instructions and the slaves to all the same. Thats 
fine for image processing, but its not possible to build a MC with this 
model.
But the real problem is the big performance gap. Softprocessor run with 
about 100 MHz. On the new Virtex-5 maybe 150 MHz. A simple softprocessor 
needs 2 cycles per instruction, giving 50-75 MIPS. There is no pipeline. One 
can build more sophisticated softprocessor, but then one can not fit a lot 
into one FPGA.
One can give this softprocessor some special purpose instructions which 
would speed up things. But there is nevertheless a big performance gap 
between 1 Pentium core and 1 softprocessor. I assume 1:10 to 1:20. So even a 
system with 128 processor would not be much faster than a Dual core.

One could theoretically such a system in hardware. But thats only 
theoretical. Its much too expensive and complicated to build such an ASIC.

Chrilly

Note: The softprocessor concept is used currently for a surprising purpose. 
Producers of consumer articles like e.g. washing machines have the problem 
that the chips for their design are not available any more and replaced by 
newer generations. But its rather costly to do a redesign. One implementes 
therefore the old chips as a softprocessor in a low cost FPGA.